1. Field of the Invention
This invention relates generally to processes for fabricating metal-oxide-semiconductor (MOS) transistors, and in particular to a new process for fabricating MOS transistors having dual gate electrodes and self-aligned contact windows for interconnects.
2. Description of the Prior Art
Semiconductor devices are constantly being miniaturized. As both semiconductor devices and lithographic line widths for making such devices become smaller and smaller, hundreds of thousands of integrated circuit (IC) components, including metal-oxide-semiconductor field-effect transistors (MOSFETs) and other metal-oxide-semiconductor (MOS) and complementary metal-oxide-semiconductor (CMOS) components, are packed onto each square centimeter of a semiconductor substrate. Thus, semiconductor technologists constantly strive to improve IC device structure and processing methods under the relentless pressure imposed by shrinking devices having ever-tightening functional requirements, e.g., lower and lower operating voltage and power consumption.
The fabrication of field-effect transistors involves the formation of n-type and p-type doped regions. As the transistor is made smaller and smaller, the formation of very shallowly doped regions, i.e., xe2x80x9cshallow junctions,xe2x80x9d become a very challenging task. Shallow junctions, when properly formed, can mitigate various undesirable effects caused by short channels, leakage current, contact resistance and sheet resistance. However, until very recently, myriads of technical difficulties have plagued the formation of shallow junctions. See, for example, U.S. Pat. No. 5,763,319, titled xe2x80x9cProcess for Fabricating Semiconductor Devices with Shallowly Doped Regions Using Dopant Compounds Containing Elements of High Solid Solubility,xe2x80x9d issued to Ling et. al. on Jun. 6, 1998.
The use of raised source and drain has recently been adopted as an alternative technique for forming a shallow junction in a field-effect transistor. Thus, landing pads are first formed at the surface regions of the substrate where the source and the drain are to be formed; meanwhile, a resist mask protects the active region where the gate electrode of the transistor is to be formed. Dopant ions are then implanted in the pads through a conventional ion implantation process. The implanted dopant ions are made to diffuse, typically by way of thermal treatment, into the designated substrate surface regions to form the raised source and drain. Subsequently, the protective resist mask is removed, and the gate electrode is formed at the active region. Various other elements of the semiconductor devices, such as the conductors and the dielectric layers, are sequentially formed on the substrate to complete the fabrication of the transistor. Finally, interconnects are formed to link up the transistors and other components of the semiconductor device.
Although recent progresses has made it easier to form field-effect transistors with raised sources and drains, the constant miniaturization of semiconductor devices dictates that other improvements be made to the formation of the transistors and the interconnects. For example, as the lithographic line width is reduced to 0.25 xcexcm or smaller (i.e., deep sub-micron), it becomes more and more difficult to control the critical dimensions of semiconductor devices through conventional exposure and etching schemes. Device miniaturization also places great strain on the device planarization requirement particularly when such devices include raised sources and drains. In short, the mere incorporation of raised source and drain in transistors is insufficient to solve all the problems associated with the fabrication of ever-shrinking semiconductor devices.
It is well-known that the function of a field-effect transistor depends to a great extent on its threshold voltage. Threshold voltage, in turn, depends on the electronic properties of the semiconductor material constituting the IC component. For example, the threshold voltage of a p-type CMOS transistor having a single dopant in its conductor may be incompatible with that of an n-type CMOS transistor also having a single dopant in its conductor, thus preventing these CMOS transistors from optimally operating together. In addition, the reduction in size of the CMOS transistors, together with the requirement for lower operating voltage and power consumption, dictates that the threshold voltages of these CMOS transistors be made as small as practicable. Hence, double dopant implantation in the gate electrode of the transistors has been proposed to help reduce the threshold voltages of the transistors.
Further, in a typical semiconductor device, hundreds of thousands or even millions of field-effect transistors are linked to one another through interconnects, which generally have to be formed on an insulator to ensure electrical insulation. The conventional process for making interconnects involves: planarizing the semiconductor structure comprising the IC components that have just been fabricated; depositing an insulating layer on the IC components; lithographically defining and forming (by, e.g., etching) contact windows for the interconnects; and depositing conductor material (by, e.g., contact metalization) to form the interconnects. As IC components are made smaller and smaller, such a process becomes more and more difficult. For example, photomask pattern shifts during contact metalization increase greatly; and etching difficulties also rise sharply. All these tend to reduce the yield of the overall IC device fabrication process.
Accordingly, it is an object of the present invention to provide a new semiconductor processing method that facilitates the formation of transistors having raised source and drain electrodes.
Another object of the present invention is to provide a method for fabricating MOS transistors with raised sources and drains and dual gate electrodes.
Still another object of the present invention is to provide a method for forming an IC device comprising transistors with self-aligned contact windows for interconnects.
In accordance with the objects described above, the present invention provides a method of fabricating an IC device comprising MOS transistors and other IC components; the transistors have raised source and drain electrodes and dual gate electrodes; and the transistors and other IC components are interconnected through the use of self-aligned contact windows. Essentially, this method comprises the following steps:
Forming on a semiconductor substrate a plurality of isolation regions to separate a plurality of active regions;
forming a well in the substrate doped with a first type of dopants;
forming a first gate structure on an active region and a second gate structure on an adjacent isolation region, either gate structure comprising a gate electrode layer of a first conductor material and a first dielectric layer; the second gate structure having a larger surface area than the first gate structure;
deposited an etch-stop layer on top of the substrate and the gate structures;
forming a second dielectric layer on those portions of the substrate that are not covered by the gate structures;
forming a mask layer on the second gate structure and on those portions of the second dielectric layer that are not next to the first gate structure;
removing those unmasked portions of the second dielectric layer next to the first gate structure to form two trenches next to the first gate structure;
removing the mask layer;
depositing a second conductor material in the two trenches to form two conductor columns;
removing the first dielectric layers of the first and second gate structures;
doping the gate electrode layers of the first and second gate structures with a second type of dopants to form the dual gate electrodes;
diffusing the second type of dopants into the substrate to form the raised source and drain electrodes;
forming side walls of a third dielectric material;
forming self-aligned silicides on the two conductor columns and the two gate electrode layers;
forming a third dielectric layer on top of the two gate electrode layers to cover the first gate electrode layer entirely and the second gate electrode layer partially and to form self-aligned contact windows; and
forming the interconnects at the contact windows to connect the conductor columns and the second gate electrode layer to other transistors and IC components on the substrate.
Essentially, the MOS fabrication process disclosed herein has the following significant advantages over those taught in the conventional art:
An advantage of the present invention is that it is more compatible with deep submicron semiconductor processes than the conventional art for forming interconnected semiconductor transistors.
Another advantage is that the IC device fabricated by the present method can be operated at a lower voltage and has lower power consumption than conventional IC devices because the transistors of the new IC device generally have lower threshold voltages.
Yet another advantage of the present invention is that it reduces planarizing difficulties during device fabrication, thus making it easier to create multilayer, multi-metalization devices.
These and other objects, features and advantages of the present invention will no doubt become apparent to those skilled in the art after reading the following detailed description of the preferred embodiment which is illustrated in the several figures of the drawing.